Dec 2022
Trainee
Router 1*3- RTL design and verification
HDL :Verilog
HVL: System Verilog
EDA Tools: Questasim and ISE
Description : The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0,channel1,channel2.
HVL: System Verilog
EDA Tools: Questasim and ISE
Description : The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0,channel1,channel2.